Computer Organisation and Architecture - Addressing Modes

Addressing Modes– The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.

Addressing modes for 8086 instructions are divided into two categories:

1) Addressing modes for data

2) Addressing modes for branch

The 8086 memory addressing modes provide flexible access to memory, allowing you to easily access variables, arrays, records, pointers, and other complex data types.  The key to good assembly language programming is the proper use of memory addressing modes.

An assembly language program instruction consists of two parts

The memory address of an operand consists of two components: 

IMPORTANT TERMS

• Starting address of memory segment.
• Effective address or Offset: An offset is determined by adding any combination of three address elements: displacement, base and index.
  • Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
  • Base: Contents of base register, BX or BP.
  • Index: Content of index register SI or DI.

According to different ways of specifying an operand by 8086 microprocessor, different addressing modes are used by 8086.

Addressing modes used by 8086 microprocessor are discussed below:

Immediate mode: In immediate addressing the operand is specified in the instruction itself. In this mode the data is 8 bits or 16 bits long and data is the part of instruction.

Example: MOV AL, 35H (move the data 35H into AL register)

Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general purpose registers. The data is in the register that is specified by the instruction.
Example: MOV AX,CX (move the contents of CX register to AX register)Register Indirect mode: In this addressing the operand’s offset is placed in any one of the registers BX,BP,SI,DI as specified in the instruction. The effective address of the data is in the base register or an index register that is specified by the instruction. The 8086 CPUs let you access memory indirectly through a register using the register indirect addressing modes.

Example: MOV AX, [BX] (move contents of memory location addressed by the register BX to the register AX)

Auto-increment mode: Effective address of the operand is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to the next consecutive memory location.

Auto-decrement mode: Effective address of the operand is the contents of a register specified in the instruction. Before accessing the operand, the contents of this register are automatically decremented to point to the previous consecutive memory location.

Direct mode: The operand’s offset is given in the instruction as an 8 bit or 16 bit displacement element. In this addressing mode the 16 bit effective address of the data is the part of the instruction.

Example: ADD AL, [0301] (add the contents of offset address 0301 to AL)

Base addressing: The operand’s offset is sum of an 8 bit or 16 bit displacement and the contents of the base register BX or BP. BX is used as a base register for data segment, and BP is used as a base register for stack segment.

Example: MOV AL,[BX+05] (suppose reg. BX contain 0301. The offset will be 0301+05=0306. Content of the memory location 0306 will move to AL)

Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI or DI and an 8 bit or 16 bit displacement.

Example: MOV AX, [SI+05]

Base Indexed addressing mode: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]

Computer Organisation and Architecture - Machine Instructions

Machine Instructions are commands or programs written in machine code of a machine (computer) that it can recognize and execute.

• A machine instruction consists of several bytes in memory that tells the processor to perform one machine operation.
• The processor looks at machine instructions in main memory one after another, and performs one machine operation for each machine instruction.
• The collection of machine instructions in main memory is called a machine language program.

Machine code or machine language is a set of instructions executed directly by a computer’s central processing unit (CPU). Each instruction performs a very specific task, such as a load, a jump, or an ALU operation on a unit of data in a CPU register or memory. Every program directly executed by a CPU is made up of a series of such instructions.

The general format of a machine instruction is

[Label:]                 Mnemonic      [Operand, Operand]                  [;Comments]

• Brackets indicate that a field is optional
• Label is an identifier that is assigned the address of the first byte of the instruction in which it appears. It must be followed by “:”
• Inclusion of spaces is arbitrary, except that at least one space must be inserted; no space would lead to an ambiguity.
• Comment field begins with a semicolon “ ; ”

Example:

Pointing:                 MOV      R5, #25H                 ;load 25H into R5

Machine instructions used in 8086 microprocessor

1. Data transfer instructions– move, load exchange, input, output.

• MOV :Move byte or word to register or memory .
• IN, OUT: Input byte or word from port, output word to port.
• LEA: Load effective address
• LDS, LES Load pointer using data segment, extra segment .
• PUSH, POP: Push word onto stack, pop word off stack.
• XCHG: Exchange byte or word.
• XLAT: Translate byte using look-up table.

2. Arithmetic instructions – add, subtract, increment, decrement, convert byte/word and compare.

• ADD, SUB: Add, subtract byte or word
• ADC, SBB :Add, subtract byte or word and carry (borrow).
• INC, DEC: Increment, decrement byte or word.
• NEG: Negate byte or word   (two’s complement).
• CMP: Compare byte or word (subtract without storing).
• MUL, DIV: Multiply, divide byte or word (unsigned).
• IMUL, IDIV: Integer multiply, divide byte or word (signed)
• CBW, CWD: Convert byte to word, word to double word
• AAA, AAS, AAM,AAD: ASCII adjust for add, sub,  mul, div .
• DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers)

3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test

• NOT :   Logical NOT of byte or word (one’s complement)
• AND:  Logical AND of byte or word
• OR: Logical OR of byte or word.
• XOR: Logical exclusive-OR of byte or word
• TEST: Test byte or word (AND without storing).
• Shift, rotate instruction- SHL, SHR Logical shift left, right byte or word? by 1or CL
• SAL, SAR Arithmetic shift left, right byte or word? by 1 or CL
• ROL, ROR Rotate left, right byte or word? by 1 or CL .
• RCL,  RCR Rotate left, right through carry byte or word? by 1 or CL.

4. String manipulation instruction – load, store, move, compare and scan for byte/word

• MOVS: Move byte or word string
• MOVSB, MOVSW: Move byte, word string.
• CMPS:  Compare byte or word string.
• SCAS S: can byte or word string (comparing to A or AX)
• LODS, STOS:  Load, store byte or word string to AL.

5. Control transfer instructions – conditional, unconditional, call subroutine and return from subroutine.

• JMP:Unconditional jump .it includes loop transfer and subroutine and interrupt instructions.

 6. Loop control instructions-

•  LOOP: Loop unconditional, count in CX, short jump to target address.
• LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to target address.
• LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX, short jump to target address.
• JCXZ: Jump if CX equals zero (used to skip code in loop).
• Subroutine and Intrrupt instructions-
• CALL, RET:  Call, return from procedure (inside or outside current segment).
• INT, INTO:  Software interrupt, interrupt if overflow.IRET: Return from interrupt.

7. Processor control instructions-

Flag manipulation:

• STC, CLC, CMC:  Set, clear, complement carry flag.
• STD, CLD:  Set, clear direction flag.STI, CLI: Set, clear interrupt enable flag.
• PUSHF, POPF: Push flags onto stack, pop flags off stack.

Computer Networking - Congestion Control

Congestion is a state occurring in network layer when the message traffic is so heavy that it slows down network response time. Effects of Congestion are as follows -

1. As delay increases, performance decreases.

2. If delay increases, retransmission occurs, making situation worse.

Congestion Control Algorithms -

1. Leaky Bucket Algorithm

2. Token Bucket Algorithm

Leaky Bucket Algorithm

Let us consider an example to understand

Imagine a bucket with a small hole in the bottom.No matter at what rate water enters the bucket, the outflow is at constant rate.When the bucket is full with water additional water entering spills over the sides and is lost.

Similarly, each network interface contains a leaky bucket and the following steps are involved in leaky bucket algorithm:

1.  When host wants to send packet, packet is thrown into the bucket.
2.  The bucket leaks at a constant rate, meaning the network interface transmits packets at a constant rate.
3.  Bursty traffic is converted to a uniform traffic by the leaky bucket.
4. In practice the bucket is a finite queue that outputs at a finite rate.

Token Bucket Algorithm

Need of token bucket Algorithm:-

The leaky bucket algorithm enforces output pattern at the average rate, no matter how bursty the traffic is. So in order to deal with the bursty traffic we need a flexible algorithm so that the data is not lost. One such algorithm is token bucket algorithm.

Steps of this algorithm can be described as follows:

1. In regular intervals tokens are thrown into the bucket.
2. The bucket has a maximum capacity.
3. If there is a ready packet, a token is removed from the bucket, and the packet is send.
4. If there is no token in the bucket, the packet cannot be send.

Let’s understand with an example,

In figure (A) we see a bucket holding three tokens, with five packets waiting to be transmitted.For a packet to be transmitted, it must capture and destroy one token. In figure (B) We see that three of the five packets have gotten through, but the other two are stuck waiting for more tokens to be generated.